Clkout Special Considerations: 1:2:1 Mode; The Baud Rate Generator Clock (Brgclk); The Synchronization Clock (Syncclk, Syncclks) - Freescale Semiconductor MPC850 User Manual

Clock Signals

14.3.1.3 CLKOUT Special Considerations: 1:2:1 Mode

To enable synchronization of a system to the EXTCLK signal while still allowing the
internal circuits of the MPC850 to operate at an increased frequency, it is necessary to
maintain synchronization of the EXTCLK and CLKOUT signal. Specifically, this operation
entails:
• input clock source EXTCLK
• internal clock of 2xEXTCLK, provided by multiplying EXTCLK by 2 in the SPLL
(by programming PLPRCR[MF]=1)
• external bus clock CLKOUT with frequency equivalent to EXTCLK, provided by
dividing GCLK2 by 2 (by programming SCCR[EBDF]=01)
This is also known as 1:2:1 mode. In this mode, in order to allow multiple devices clocked
by the same EXTCLK source to maintain synchronization on the external bus, EXTCLK
and CLKOUT must be in phase. This operation cannot be guaranteed on MPC850s prior to
revision B. On MPC850s of revision B or later, this operation can be guaranteed, but it
requires that SCCR[EBDF] be written first, followed by the write to PLPRCR[MF].

14.3.1.4 The Baud Rate Generator Clock (BRGCLK)

The baud rate generator clock (BRGCLK) is used by the four baud rate generators of the
communication processor module and by the memory controller refresh counter. The baud
rate generator clock is controlled independently in order to allow the baud rate generators
and memory refresh rate to continue operating at a fixed frequency, even when the rest of
the MPC850 is operating at a reduced frequency.
BRGCLK defaults to VCOOUT, but can be reduced in frequency by a frequency divider.
This frequency divider is controlled by SCCR[DFBRG].
VCOOUT
The baud rate generator clock frequency is:
VCOOUT freq
BRGCLK freq = ------------------------------------------ -
2 DFBRG ×
2
(

14.3.1.5 The Synchronization Clock (SYNCCLK, SYNCCLKS)

The synchronization clock signals (SYNCCLK and SYNCCLKS, referred to collectively
as SYNCCLK) are used by the signal synchronization circuitry in the serial ports of the
communication processor module. The signal synchronization circuitry is used to sample
DFBRG
Figure 14-10. BRGCLK Divider
)
MPC850 Family User's Manual
CPM and
BRGCLK
(Refresh
Timer)
UPM