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RPF —Reception-in-Progress Flag
This read-only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit
search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false start
bits (usually from noise or a baud rate mismatch, or when the receiver detects an idle character. Polling
RPF before disabling the SCI module or entering stop mode can show whether a reception is in
progress.
1 = Reception in progress
0 = No reception in progress
13.7.6 SCI Data Register
The SCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit
shift registers. Reset has no effect on data in the SCI data register.
Address:
$003D
Read:
Write:
Reset:
R7/T7:R0/T0 — Receive/Transmit Data Bits
Reading address $003D accesses the read-only received data bits, R7:R0. Writing to address $003D
writes the data to be transmitted, T7:T0. Reset has no effect on the SCI data register.
13.7.7 SCI Baud Rate Register
The baud rate register (SCBR) selects the baud rate for both the receiver and the transmitter.
Address:
$003E
Read:
Write:
Reset:
SCP1 and SCP0 — SCI Baud Rate Prescaler Bits
These read/write bits select the baud rate prescaler divisor as shown in
and SCP0.
Freescale Semiconductor
Bit 7
6
5
R7
R6
R5
T7
T6
T5
Figure 13-14. SCI Data Register (SCDR)
Bit 7
6
5
0
0
SCP1
R
R
0
0
0
R
= Reserved
Figure 13-15. SCI Baud Rate Register (SCBR)
Table 13-5. SCI Baud Rate Prescaling
SCP1:SCP0
00
01
10
11
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
4
3
2
R4
R3
R2
T4
T3
T2
Unaffected by reset
4
3
2
0
SCP0
SCR2
R
0
0
0
Prescaler Divisor (PD)
1
3
4
13
I/O Registers
1
Bit 0
R1
R0
T1
T0
1
Bit 0
SCR1
SCR0
0
0
Table
13-5. Reset clears SCP1
177
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