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Synchronous Serial Interface (SSI)
16 bits
20 bits
24 bits
SSI_RXD
Figure 25-11. Receive Data Path (RXBIT0=0, RSHFD=1) (msb Alignment)
31
24 bits
31
RXSR
Figure 25-12. Receive Data Path (RXBIT0=1, RSHFD=0) (lsb Alignment)
31
31
SSI_RXD
Figure 25-13. Receive Data Path (RXBIT0=1, RSHFD=1) (lsb Alignment)
25.3.7
SSI Control Register (SSI_CR)
The SSI control register sets up the SSI modules. SSI operating modes are selected in this register (except
AC97 mode, which is selected in SSI_ACR register).
25-12
31
31
16 bits
23
19
16 bits
20 bits
23
19
23
20 bits
24 bits
23
24 bits
MCF52277 Reference Manual, Rev. 1
15
11
12 bits
15
11
12 bits
15
11
12 bits
15
11
19
15
11
12 bits
16 bits
19
15
11
20 bits
16 bits
12 bits
7
0
SSI_RX
7
0
RXSR
0
SSI_RX
SSI_RX
0
24 bits
0
0
Freescale Semiconductor
SSI_RXD
SSI_RX
RXSR
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