Memory Map/Register Definition; Mac Status Register (Macsr) - Freescale Semiconductor MCF5329 Reference Manual

4.2

Memory Map/Register Definition

The following table and sections explain the MAC registers:
1
BDM
0x804

MAC Status Register (MACSR)

0x805 MAC Address Mask Register (MASK)
0x806 MAC Accumulator 0 (ACC0)
0x807 MAC Accumulator 0,1 Extension Bytes (ACCext01)
0x808 MAC Accumulator 2,3 Extension Bytes (ACCext23)
0x809 MAC Accumulator 1 (ACC1)
0x80A MAC Accumulator 2 (ACC2)
0x80B MAC Accumulator 3 (ACC3)
1
The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more
information see Chapter 36, "Debug Module."
4.2.1 MAC Status Register (MACSR)
The MAC status register (MACSR) contains a 4-bit operational mode field and condition flags.
Operational mode bits control whether operands are signed or unsigned and whether they are treated as
integers or fractions. These bits also control the overflow/saturation mode and the way in which rounding
is performed. Negative, zero, and multiple overflow condition flags are also provided.
BDM: 0x804 (MACSR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–12 Reserved, must be cleared.
11–8 Product/accumulation overflow flags. Contains four flags, one per accumulator, that indicate if past MAC or
PAVn MSAC instructions generated an overflow during product calculation or the 48-bit accumulation. When a
MAC or MSAC instruction is executed, the PAVn flag associated with the destination accumulator is used
to form the general overflow flag, MACSR[V]. Once set, each flag remains set until V is cleared by a
move.l, MACSR instruction or the accumulator is loaded directly.
Freescale Semiconductor
Table 4-1. EMAC Memory Map
Register
Figure 4-2. MAC Status Register (MACSR)
Table 4-2. MACSR Field Descriptions
Description
MCF5329 Reference Manual, Rev 3
Enhanced Multiply-Accumulate Unit (EMAC)
Width
Access Reset Value
(bits)
32 R/W 0x0000_0000
32 R/W 0xFFFF_FFFF
32 R/W Undefined
32 R/W Undefined
32 R/W Undefined
32 R/W Undefined
32 R/W Undefined
32 R/W Undefined
Access: Supervisor read/write
8 7 6 5
PAVn OMC S/U F/I
0 0 0
Section/Page
4.2.1/4-3
4.2.2/4-5
4.2.3/4-6
4.2.4/4-7
4.2.4/4-7
4.2.3/4-6
4.2.3/4-6
4.2.3/4-6
BDM read/write
4 3 2 1 0
R/T N Z V EV
0 0 0 0 0
4-3