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the original value written except for the DATA field whose contents are replaced by the value read from
the PHY register.
If the MMFR register is written while frame generation is in progress, the frame contents are altered.
Software must use the MII interrupt to avoid writing to the MMFR register while frame generation is in
progress.
19.4.8
MII Speed Control Register (MSCR)
The MSCR provides control of the MII clock (FEC_MDC pin) frequency and allows a preamble drop on
the MII management frame.
Address: 0xFC03_0044
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIS_
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–8
Reserved, must be cleared.
7
Setting this bit causes the preamble (32 ones) not to be prepended to the MII management frame. The MII
DIS_PRE
standard allows the preamble to be dropped if the attached PHY device(s) does not require it.
6–1
Controls the frequency of the MII management interface clock (FEC_MDC) relative to the internal bus clock. A
MII_SPEED
value of 0 in this field turns off the FEC_MDC and leaves it in low voltage state. Any non-zero value results in the
FEC_MDC frequency of 1/(MII_SPEED × 2) of the internal bus frequency.
0
Reserved, must be cleared.
The MII_SPEED field must be programmed with a value to provide an FEC_MDC frequency of less than
or equal to 2.5 MHz to be compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set
to a non-zero value to source a read or write management frame. After the management frame is complete,
the MSCR register may optionally be set to 0 to turn off the FEC_MDC. The FEC_MDC generated has a
50% duty cycle except when MII_SPEED changes during operation (change takes effect following a rising
or falling edge of FEC_MDC).
If the internal bus clock is 25 MHz, programming this register to 0x0000_0005 results in an FEC_MDC
as stated the equation below.
A table showing optimum values for MII_SPEED as a function of internal bus clock frequency is provided
below.
Freescale Semiconductor
Figure 19-8. MII Speed Control Register (MSCR)
Table 19-11. MSCR Field Descriptions
Description
1
×
----------- -
25 MHz
=
2.5 MHz
×
5
2
MCF5329 Reference Manual, Rev 3
Fast Ethernet Controller (FEC)
Access: User read/write
8
7
6
5
4
3
2
1
0
0
MII_SPEED
PRE
0
0 0 0 0 0 0 0
Eqn. 19-1
19-15
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