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SPI Signal Description
17.1.2
Modes of Operation
The SPI functions in the following three modes:
•
Run Mode—The normal mode of operation.
•
Wait Mode—The SPI can be configured to operate in low-power mode. Based on the internal bit state, the SPI can operate normally
when the CPU is in wait mode or the SPI clock generation can be turned off and the SPI module enters a power conservation state
during wait mode. During wait mode, any master transmission in progress stops. Transmission and reception resumes when the SPI
exits wait mode.
•
Stop Mode—This mode is system dependent. The SPI enters the stop mode when the module clock is disabled (held high or low).
If the SPI is in master mode and exchanging data when the processor enters stop mode, the transmission stops until the processor
exits stop mode.
17.2
SPI Signal Description
Table 17-1
shows external SPI signals and their properties. These signals may connect off-chip. Detailed signal descriptions are given in the
sections below.
Signal Name
MISO
MOSI
SCK
SS
Note:
1. SPI ports MISO, MOSI, SCK, and SS are GPIO ports when SPI is disabled (SPE=0).
17.2.1
Master In/Slave Out (MISO)
MISO is one of two SPI module pins that transmit serial data. MISO is an input when the SPI is configured as a master and an output when
the SPI is configured as a slave.
If the bidirectional serial pin mode is selected as a slave, MISO becomes a slave in/slave out (SISO) and the direction is controlled by the
associated bit in the SPI port data direction register.
In a multiple-master system, all MISO pins are tied together.
17.2.2
Master Out/Slave In (MOSI)
MOSI is one of two SPI module pins that transmit serial data. MOSI is an output when the SPI is configured as a master and an input when
the SPI is configured as a slave.
If the bidirectional serial pin mode is selected as a master, MOSI becomes master out/master in (MOMI) and the direction is controlled by the
associated bit in the SPI port data direction register.
In a multiple-master system, all MOSI pins are tied together.
17.2.3
Serial Clock (SCK)
The serial clock synchronizes data transmissions between master and slave devices. SCK is an output if the SPI is configured as a master and
SCK is an input if the SPI is configured as a slave.
In master mode the Serial Clock is derived from the IPB clock.
In a multiple-master system, all SCK pins are tied together.
17.2.4
Slave-Select (SS)
The slave-select output or input provides a means of selectively enabling slaves so several may coexist in one system. SS is either a
general-purpose output (SSOE = 0) or the slave select output (SSOE = 1) when the SPI is in master mode and the associated data direction
bit is set.
17-2
Table 17-1. SPI External Signal Descriptions
Port
SPIPORT[7]
Master Data In/Slave Data Out
SPIPORT[6]
Master Data Out/Slave Data In
SPIPORT[5]
SPIPORT[4]
MPC5200B Users Guide, Rev. 1
Function1
Serial Clock
Slave Select
Reset State
0
0
0
0
Freescale Semiconductor
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