Block Diagram; External Signal Description; Sdram Data Bus (Sddata[31:0]); Sdram Address Bus (Sdaddr[12:0]) - Freescale Semiconductor MCF5480 Reference Manual

18.2.3

Block Diagram

addr[29:4]
18.3

External Signal Description

18.3.1

SDRAM Data Bus (SDDATA[31:0])

SDDATA[31:0] is the bidirectional, non-multiplexed data bus used for SDRAM accesses. Data is sampled
by the MCF548x on the rising edge of SDCLK when in SDR mode, and on both the rising and falling edge
of SDCLK when in DDR mode.
18.3.2

SDRAM Address Bus (SDADDR[12:0])

The SDADDR[12:0] signals are the 13-bit, uni-directional address bus used for multiplexed row and
column addresses during SDRAM bus cycles. The address multiplexing supports up to 256 Mbytes of
SDRAM per chip select.
18.3.3

SDRAM Bank Addresses (SDBA[1:0])

Each SDRAM module has four internal row banks. The SDBA[1:0] signals are used to select the row bank.
It is also used to select the SDRAM internal mode register during power-up initialization.
18-2
Column
Address
Bank
Input
MUX
Row
addr[1:3]
tsiz[1:0], tbst
datain[63:0]
dataout[63:0]
Figure 18-1. SDRAM Controller Block Diagram
MCF548x Reference Manual, Rev. 3
Column
Address
Bank
Pipeline
Latches
Row
Select
SDCS[3:0]
RAS
SDRAM
CAS
Controller
State
SDWE
Machine
SDDQS
SDCLK[1:0]
SDCLK[1:0]
SDCKE
SDDM
SDDATA[31:0]
Write Data
Buffer
SDDATA[31:0]
Read Data
Buffer
SDADDR[12:0]
Address
Output
SDBA[1:0]
MUX
Freescale Semiconductor