Port A Data Direction Register (Padir); Port A Pin Assignment Register (Papar) - Freescale Semiconductor MPC850 User Manual

Port A
Table 34-3 describes PADAT bits.
Bits Name
0–3, 10–11 —
4–9, 12–15 Dn

34.2.1.3 Port A Data Direction Register (PADIR)

Port A data direction register (PADIR) bits configure port A signals as general-purpose
inputs or outputs. If a signal is not programmed for general-purpose I/O, PADIR selects the
peripheral function to be performed.
Bit 0 1 2
Field — — —
Reset — — —
R/W
Addr
Figure 34-3. Port A Data Direction Register (PADIR)
Table 34-4 describes PADIR bits.
Bits Name
0–3, — Reserved
10–11
4–9, DRn Port A data direction. Configures port A signals as inputs or outputs when functioning as
12–15 general-purpose I/O; otherwise, used to select the peripheral function.
0 Select the signal for general-purpose input, or select peripheral function 0.
1 Select the signal for general-purpose output, or select peripheral function 1.

34.2.1.4 Port A Pin Assignment Register (PAPAR)

The port A pin assignment register (PAPAR) configures signals as general-purpose I/O or
dedicated for use with a peripheral.
Bit 0 1 2
Field — — —
Reset — — —
R/W
Addr
Figure 34-4. Port A Pin Assignment Register (PAPAR)
Table 34-3. PADAT Bit Descriptions
Reserved
Contains the data on the corresponding signal.
3 4 5 6
— DR4 DR5 DR6 DR7 DR8 DR9
— 0 0 0
R/W R/W R/W R/W R/W R/W
Table 34-4. PADIR Bit Descriptions
3 4 5 6
— DD4 DD5 DD6 DD7 DD8 DD9
— 0 0 0
R/W R/W R/W R/W R/W R/W
MPC850 Family User's Manual
Description
7 8 9 10
—
0 0 0 —
0x950
Description
7 8 9 10
—
0 0 0 —
0x952
11 12 13 14
— DR12 DR13 DR14 DR15
— 0 0 0
R/W R/W R/W
11 12 13 14
— DD12 DD13 DD14 DD15
— 0 0 0
R/W R/W R/W
15
0
R/W
15
0
R/W