Pll Pre-Divider Factor (Pd0-Pd4); Pll Multiplication Factor (Mf0-Mf7); Pll Feedback Multiplier (Od1); Pll Output Divide Factor (Od0-Od1) - Freescale Semiconductor DSP56374 User Manual

Device Identification (ID) Register

T
11
X:$FFFFFD
23
4.6.1

PLL Pre-Divider Factor (PD0-PD4)

The DSP56374 PLL Pre-Divider factor is set to 4 during hardware reset, i.e., the Pre-Divider Factor Bits PD0-PD4 in the PLL Control Register
(PCTL) are set to $4.
4.6.2

PLL Multiplication Factor (MF0-MF7)

The DSP56374 PLL multiplication factor is set to 29 during hardware reset, i.e., the Multiplication Factor Bits MF0-MF7 in the PLL Control
Register (PCTL) are set to $1D.
4.6.3

PLL Feedback Multiplier (OD1)

The DSP56374 PLL Feedback Multiplier is set to 2 during hardware reset, i.e., OD1 is cleared ($0) in the PLL Control Register (PCTL).
4.6.4

PLL Output Divide Factor (OD0-OD1)

The DSP56374 PLL Output Divider factor is set to 2 during hardware reset, i.e., OD1 is cleared ($0) and OD0 is set ($1) in the PLL Control
Register (PCTL).
4.6.5

PLL Divider Factor (DF0-DF2)

The DSP56374 PLL Divider factor is set to 1 during hardware reset, i.e., the Divider Factor Bits DF0-DF2 in the PLL Control Register (PCTL)
are set to $0.
4.6.6

PLL LOCK MUX (PLKM)

The PLOCK Mux (PLKM) bit is a read/write bit that controls the operation of the PLOCK/TIO2 pin. When PLKM is set, the PLOCK/TIO2
pin operates as the PLL lock indicator (PLOCK). When the PLKM bit is cleared, the PLOCK/TIO2 pin operates as the TIO2 pin.
Note: The PLKM bit is set during hardware reset.
4.7 Device Identification (ID) Register
The Device Identification Register (IDR) is a 24 bit read only factory programmed register used to identify the different DSP56300 core-based
family members located at x:$FFFFF5. This register specifies the derivative number and revision number. This information may be used in
testing or by software. Table 4-6
23
Reserved
4.8

JTAG Identification (ID) Register

The JTAG Identification (ID) Register is a 32 bit, read only thought JTAG, factory programmed register used to distinguish the component on
a board according to the IEEE 1149.1 standard.
4-6
10 9 8 7
DF2 DF1 DF0 MF7
22 21 20 19
PLKM PD4 PD3
Figure 4-3. PCTL Register
shows the ID register configuration.
Table 4-6. Identification Register Configuration
16 15 12
Revision Number
$00 $0
Table 4-7 shows the JTAG ID register configuration.
DSP56374 Users Guide, Rev. 1.2
6 5 4 3
MF6 MF5 MF4 MF3
18 17 16 15
PD2 PD1 PD0 OD1
11
Derivative Number
$374
2 1 0
MF2 MF1 MF0
14 13 12
OD0 PEN PSTP
0
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