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Power Management
Field
6
Set all module clock disables.
SAMCD
0 Set only those bits specified in the SMCD field
1 Set all bits in PPMRH and PPMRL, disabling all peripheral clocks
5–0
Set module clock disable. Set the corresponding bit in PPM{H,L}R, disabling the peripheral clock.
SMCD
8.2.3
Peripheral Power Management Clear Registers (PPMCR0 &
PPMCR1)
The PPMCR registers provide a simple mechanism to clear a given bit in the PPMHR & PPMLR registers,
enabling the clock for a given peripheral module without the need to perform a read-modify write on the
PPMR. The data value on a register write causes the corresponding bit in the PPM{H,L}R to be clear. A
value of 64 to 127 (setting the CAMCD bit) provides a global clear function forcing the entire contents of
the PPMR to be clear, enabling all peripheral module clocks. Reads of these registers return all zeroes.
Address: 0xFC04_002D (PPMCR0)
0xFC04_002F (PPMCR1)
7
R
0
W
Reset:
0
Figure 8-3. Peripheral Power Management Clear Registers (PPMCRn)
Field
7
Reserved, should be cleared.
6
Clear all module clock disables.
CAMCD
0 Clear only those bits specified in the CMCD field
1 Clear all bits in PPMRH and PPMRL, enabling all peripheral clocks
5–0
Clear module clock disable. Clear the corresponding bit in PPMR{H,L}, enabling the peripheral clock.
CMCD
8.2.4
Peripheral Power Management Registers (PPMHR0, PPMHR1, &
PPMLR0)
The PPMR registers provide a bit map for controlling the generation of the peripheral clocks for each
decoded address space. Recall each peripheral module is mapped into 16 kByte slots within the memory
map. The PPMR registers provide a unique control bit for each of these address spaces that defines whether
the module clock for the given space is enabled or disabled.
8-4
Table 8-3. PPMSRn Field Descriptions (continued)
6
5
0
0
CAMCD
0
0
Table 8-4. PPMCRn Field Descriptions
MCF5329 Reference Manual, Rev 3
Description
4
3
2
0
0
0
CMCD
0
0
0
Description
Access: Supervisor Write-only
1
0
0
0
0
0
Freescale Semiconductor
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