Ictl Peripheral Interrupt Status All Register—Mbar + 0X0530 - Freescale Semiconductor MPC5200B User Manual

Interrupt Controller
Bits Name
16 PSa6
17 PSa7
18 PSa8
19 PSa9
20 PSa10
21 PSa11
22 PSa12
23 PSa13
24 PSa14
25 PSa15
26 PSa16
27 PSa17
28 PSa18
29:30 —
31 PSa21
Note:
1. These interrupts are directly maskable by ICTL Peripheral Interrupt Mask Register. However, PSa status occurs
regardless of Per_Mask setting, as long as the source module interrupt is enabled in the source module registers.
7.2.4.13 ICTL Peripheral Interrupt Status All Register—MBAR + 0x0538
msb 0 1
R
W
RESET: 0 0
16 17
R
W
RESET: 0 0
Bits Name
0:5 — Reserved
6 BE1 Bus Error 1—Indicates write attempt to read-only register, clear with a write to 1.
7 BE2 Bus Error 0—Indicates access to unimplemented register, clear with a write to 1.
8:31 — Reserved
7-18
USB
ATA
PCI Control module
PCI SC Initiator Rx
PCI SC Initiator Tx
PSC4
PSC5
SPI modf
SPI spif
2
I C1
2
I C2
CAN1
CAN2
Reserved
XLB Arbiter
Table 7-16. ICTL Bus Error Status Register
2 3 4 5 6
Reserved BE1
0 0 0 0 0
18 19 20 21 22
0 0 0 0 0
MPC5200B Users Guide, Rev. 1
Description
7 8 9 10
BE0
0 0 0 0
23 24 25 26
Reserved
0 0 0 0
Description
11 12 13 14 15
Reserved
0 0 0 0
27 28 29 30 31 lsb
0 0 0 0
Freescale Semiconductor
0
0