Renesas H8SX/1520 Series Hardware Manual page 614

Section 17 Flash Memory (0.18-(m F-ZTAT Version)
(1)
Selection of On-Chip Program to be Downloaded
For programming/erasing, the FLSHE bit in the system control register (SYSCR) must be set to 1
to select user program mode. This LSI has programming/erasing programs which can be
downloaded to the on-chip RAM. The on-chip program to be downloaded is selected by the
programming/erasing interface registers. The start address of the on-chip RAM where an on-chip
program is downloaded is specified by the flash transfer destination address register (FTDAR).
(2)
Download of On-Chip Program
The on-chip program is automatically downloaded by setting the flash key code register (FKEY)
and the SCO bit in the flash code control/status register (FCCS) after initializing the vector base
register (VBR). The memory MAT is replaced with the embedded program storage area during
download. Since the memory MAT cannot be read during programming/erasing, the procedure
program must be executed in a space other than the flash memory (for example, on-chip RAM).
Since the download result is returned to the programming/erasing interface parameter, whether
download is normally executed or not can be confirmed. The VBR contents can be changed after
completion of download.
(3)
Initialization of Programming/Erasing
A pulse with the specified period must be applied when programming or erasing. The specified
pulse width is made by the method in which wait loop is configured by the CPU instruction.
Accordingly, the operating frequency of the CPU needs to be set before programming/erasing. The
operating frequency of the CPU is set by the programming/erasing interface parameter.
(4)
Execution of Programming/Erasing
For programming/erasing, the FLSHE bit in SYSCR must be set to 1 to make a transition to user
program mode. The start address of the programming destination and the program data are
specified in 128-byte units when programming. The block to be erased is specified with the erase
block number in erase-block units when erasing. Specifications of the start address of the
programming destination, program data, and erase block number are performed by the
programming/erasing interface parameters, and the on-chip program is initiated. The on-chip
program is executed by using the JSR or BSR instruction and executing the subroutine call of the
specified address in the on-chip RAM. The execution result is returned to the
programming/erasing interface parameter.
The area to be programmed must be erased in advance when programming flash memory. All
interrupts are disabled during programming/erasing.
Rev. 3.00 Mar. 14, 2006 Page 576 of 804
REJ09B0104-0300
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