Renesas H8SX/1520 Series Hardware Manual page 421

Bit Bit Name
5 PE
4 O/E
3 STOP
2 MP
1 CKS1
0 CKS0
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Initial
Value R/W Description
0 R/W Parity Enable (valid only in asynchronous mode)
When this bit is set to 1, the parity bit is added to transmit
data before transmission, and the parity bit is checked in
reception. For a multiprocessor format, parity bit addition
and checking are not performed regardless of the PE bit
setting.
0 R/W Parity Mode (valid only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
0 R/W Stop Bit Length (valid only in asynchronous mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
In reception, only the first stop bit is checked. If the
second stop bit is 0, it is treated as the start bit of the next
transmit frame.
0 R/W Multiprocessor Mode (valid only in asynchronous mode)
When this bit is set to 1, the multiprocessor function is
enabled. The PE bit and O/E bit settings are invalid in
multiprocessor mode.
0 R/W Clock Select 1, 0
0 R/W These bits select the clock source for the baud rate
generator.
00: Pφ clock (n = 0)
01: Pφ/4 clock (n = 1)
10: Pφ/16 clock (n = 2)
11: Pφ/64 clock (n = 3)
For the relation between the settings of these bits and the
baud rate, see section 12.3.9, Bit Rate Register (BRR). n
is the decimal display of the value of n in BRR (see
section 12.3.9, Bit Rate Register (BRR)).
Section 12 Serial Communication Interface (SCI)
Rev. 3.00 Mar. 14, 2006 Page 383 of 804
REJ09B0104-0300