Renesas H8SX/1520 Series Hardware Manual page 192

Section 7 DMA Controller (DMAC)
Bit Bit Name
12 SARA4
11 SARA3
10 SARA2
9 SARA1
8 SARA0
7 DARIE
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Initial
Value R/W Description
0 R/W Source Address Extended Repeat Area
0 R/W Specify the extended repeat area on the source address
(DSAR). With the extended repeat area, the specified
0 R/W
lower address bits are updated and the remaining upper
0 R/W
address bits are fixed. The extended repeat area size is
specified from four bytes to 128 Mbytes in units of byte
0 R/W
and a power of 2.
When the lower address is overflowed from the
extended repeat area by address update, the address
becomes the start address and the end address of the
area for address addition and subtraction, respectively.
When an overflow in the extended repeat area occurs
with the SARIE bit set to 1, an interrupt can be
requested. Table 7.2 shows the settings and areas of
the extended repeat area.
0 R/W Destination Address Extended Repeat Area Overflow
Interrupt Enable
Enables/disables an interrupt request for an extended
area overflow on the destination address.
When an extended repeat area overflow on the
destination address occurs while this bit is set to 1, the
DTE bit in DMDR is cleared to 0. At this time, the ESIF
bit in DMDR is set to 1 to indicate an interrupt by an
extended repeat area overflow on the destination
address is requested.
When block transfer mode is used with the extended
repeat area function, an interrupt is requested after
completion of a 1-block size transfer. When setting the
DTE bit in DMDR of the channel for which the transfer
has been stopped to 1, the transfer is resumed from the
state when the transfer is stopped.
When the extended repeat area is not specified, this bit
is ignored.
0: Disables an interrupt request for an extended area
1: Enables an interrupt request for an extended area
All 0 R Reserved
These are read-only bits and cannot be modified.
overflow on the destination address
overflow on the destination address