Renesas H8SX/1520 Series Hardware Manual page 424

Section 12 Serial Communication Interface (SCI)
Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0):
Bit Bit Name
7 TIE
6 RIE
5 TE
4 RE
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Initial
Value R/W Description
0 R/W Transmit Interrupt Enable
When this bit is set to 1, a TXI interrupt request is
enabled.
A TXI interrupt request can be cancelled by reading 1
from the TDRE flag and then clearing the flag to 0, or by
clearing the TIE bit to 0.
0 R/W Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
RXI and ERI interrupt requests can be cancelled by
reading 1 from the RDRF, FER, PER, or ORER flag and
then clearing the flag to 0, or by clearing the RIE bit to 0.
0 R/W Transmit Enable
When this bit is set to 1, transmission is enabled. Under
this condition, serial transmission is started by writing
transmit data to TDR, and clearing the TDRE flag in SSR
to 0. Note that SMR should be set prior to setting the TE
bit to 1 Sin order to designate the transmission format.
If transmission is halted by clearing this bit to 0, the
TDRE flag in SSR is fixed 1.
0 R/W Receive Enable
When this bit is set to 1, reception is enabled. Under this
condition, serial reception is started by detecting the start
bit in asynchronous mode or the synchronous clock input
in clocked synchronous mode. Note that SMR should be
set prior to setting the RE bit to 1 in order to designate
the reception format.
Even if reception is halted by clearing this bit to 0, the
RDRF, FER, PER, and ORER flags are not affected and
the previous value is retained.