Renesas H8SX/1520 Series Hardware Manual page 12

Section 6 Bus Controller (BSC) ........................................................................ 125
6.1 Features.............................................................................................................................. 125
6.2 Register Descriptions......................................................................................................... 126
6.2.1
6.3 Bus Configuration.............................................................................................................. 127
6.4 Multi-Clock Function ........................................................................................................ 128
6.5 Internal Bus........................................................................................................................ 129
6.5.1
6.6 Write Data Buffer Function ............................................................................................... 130
6.6.1
6.7 Bus Arbitration .................................................................................................................. 131
6.7.1
6.7.2
6.8 Bus Controller Operation in Reset ..................................................................................... 132
6.9 Usage Notes ....................................................................................................................... 132
Section 7 DMA Controller (DMAC)................................................................. 133
7.1 Features.............................................................................................................................. 133
7.2 Register Descriptions......................................................................................................... 136
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.3 Transfer Modes .................................................................................................................. 157
7.4 Operations.......................................................................................................................... 158
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.4.10 Bus Cycles in Dual Address Mode ....................................................................... 183
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Bus Control Register 2 (BCR2) ............................................................................ 126
Access to Internal Address Space ......................................................................... 129
Write Data Buffer Function for Peripheral Module ............................................... 130
Operation .............................................................................................................. 131
Bus Transfer Timing............................................................................................. 131
DMA Source Address Register (DSAR) .............................................................. 137
DMA Destination Address Register (DDAR) ...................................................... 138
DMA Offset Register (DOFR).............................................................................. 139
DMA Transfer Count Register (DTCR) ............................................................... 140
DMA Block Size Register (DBSR) ...................................................................... 141
DMA Mode Control Register (DMDR)................................................................ 142
DMA Address Control Register (DACR)............................................................. 151
DMA Module Request Select Register (DMRSR) ............................................... 157
Address Modes ..................................................................................................... 158
Transfer Modes..................................................................................................... 162
Activation Sources................................................................................................ 166
Bus Access Modes................................................................................................ 168
Extended Repeat Area Function ........................................................................... 170
Address Update Function using Offset ................................................................. 172
Register during DMA Transfer............................................................................. 176
Priority of Channels.............................................................................................. 181
DMA Basic Bus Cycle.......................................................................................... 182