Renesas H8SX/1520 Series Hardware Manual page 742

Section 20 List of Registers
Register Name
DMA source address
register_1
DMA destination address
register_1
DMA offset register_1
DMA transfer count register_1 DTCR_1
DMA block size register_1
DMA mode control register_1
DMA address control
register_1
DMA source address
register_2
DMA destination address
register_2
DMA offset register_2
DMA transfer count register_2 DTCR_2
DMA block size register_2
DMA mode control register_2
DMA address control
register_2
DMA source address
register_3
DMA destination address
register_3
DMA offset register_3
DMA transfer count register_3 DTCR_3
DMA block size register_3
DMA mode control register_3
DMA address control
register_3
Rev. 3.00 Mar. 14, 2006 Page 704 of 804
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Number
Abbr. of Bits
DSAR_1 32
DDAR_1 32
DOFR_1 32
32
DBSR_1 32
DMDR_1 32
DACR_1 32
DSAR_2 32
DDAR_2 32
DOFR_2 32
32
DBSR_2 32
DMDR_2 32
DACR_2 32
DSAR_3 32
DDAR_3 32
DOFR_3 32
32
DBSR_3 32
DMDR_3 32
DACR_3 32
Address Module
H'FFC20 DMAC_1
H'FFC24 DMAC_1
H'FFC28 DMAC_1
H'FFC2C DMAC_1
H'FFC30 DMAC_1
H'FFC34 DMAC_1
H'FFC38 DMAC_1
H'FFC40 DMAC_2
H'FFC44 DMAC_2
H'FFC48 DMAC_2
H'FFC4C DMAC_2
H'FFC50 DMAC_2
H'FFC54 DMAC_2
H'FFC58 DMAC_2
H'FFC60 DMAC_3
H'FFC64 DMAC_3
H'FFC68 DMAC_3
H'FFC6C DMAC_3
H'FFC70 DMAC_3
H'FFC74 DMAC_3
H'FFC78 DMAC_3
Access
Data Cycles
Width (Read/Write)
16 2Iφ/2Iφ
16 2Iφ/2Iφ
16 2Iφ/2Iφ
16 2Iφ/2Iφ
16 2Iφ/2Iφ
16 2Iφ/2Iφ
16 2Iφ/2Iφ
16 2Iφ/2Iφ
16 2Iφ/2Iφ
16 2Iφ/2Iφ
16 2Iφ/2Iφ
16 2Iφ/2Iφ
16 2Iφ/2Iφ
16 2Iφ/2Iφ
16 2Iφ/2Iφ
16 2Iφ/2Iφ
16 2Iφ/2Iφ
16 2Iφ/2Iφ
16 2Iφ/2Iφ
16 2Iφ/2Iφ
16 2Iφ/2Iφ