Renesas H8SX/1520 Series Hardware Manual page 151

7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
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Yes
No
IRQ0
Yes
Branch to interrupt handling routine
Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 0
Program execution state
Interrupt generated?
Yes
NMI
No
I = 0
Yes
No
IRQ1
Yes
Save PC and CCR
I ← 1
Read vector address
Section 5 Interrupt Controller
No
No
Pending
SSTXI2
Yes
Rev. 3.00 Mar. 14, 2006 Page 113 of 804
REJ09B0104-0300