Renesas H8SX/1520 Series Hardware Manual page 172

Section 7 DMA Controller (DMAC)
• Address update can be selected from fixed address, offset addition, and increment or
decrement by 1, 2, or 4
Address update by offset addition enables to transfer data at addresses which are not placed
continuously
• Word or longword data can be transferred to an address which is not aligned with the
respective boundary
Data is divided according to its address (byte or word) when it is transferred
• Two types of interrupts can be requested to the CPU
A transfer end interrupt is generated after the number of data specified by the transfer counter
is transferred. A transfer escape end interrupt is generated when the remaining total transfer
size is less than the transfer data size at a single transfer request, when the repeat size of data
transfer is completed, or when the extended repeat area overflows.
Note: * An external request and single address mode are not supported by the H8SX/1520
Group.
Rev. 3.00 Mar. 14, 2006 Page 134 of 804
REJ09B0104-0300
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