Renesas H8SX/1520 Series Hardware Manual page 701

Bit Bit Name
13 POSEL1

12, 11
10 ICK2
9 ICK1
8 ICK0

7
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Initial
Value R/W Description
B φ Output Select 1
0 R/W
Controls the B φ output on PA7.
0: External clock (Bφ)
1: Setting prohibited
All 0 R/W Reserved
These bits are always read as 0. The write value should
always be 0.
0 R/W System Clock (Iφ) Select
1 R/W These bits select the frequency of the system clock
provided to the CPU and DMAC. The ratio to the input
0 R/W
clock is as follows:
000: ×8
001: ×4
010: ×2
011: ×1
1XX: Setting prohibited
The frequency of the peripheral module clock changes to
the same frequency as the system clock if the frequency
of the system clock is lower than that of the peripheral
module clock.
0 R/W Reserved
This bit is always read as 0. The write value should
always be 0.
Section 18 Clock Pulse Generator
Rev. 3.00 Mar. 14, 2006 Page 663 of 804
REJ09B0104-0300