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PPG
Pulse output delay time
SCI
Input clock
cycle
Input clock pulse width
Input clock rise time
Input clock fall time
Output clock
cycle
Output clock pulse width
Output clock rise time
Output clock fall time
Transmit data delay time
Receive data setup time
(clocked synchronous)
Receive data hold time
(clocked synchronous)
A/D
Trigger input setup time
converter
Downloaded from
Elcodis.com
electronic components distributor
Item
Asynchronous
Clocked
synchronous
Asynchronous
Clocked
synchronous
Symbol
Min.
Max.
t
40
POD
t
4
Scyc
6
t
0.4
0.6
SCKW
t
20
SCKr
t
20
SCKf
t
30
Scyc
4
t
0.6
0.4
SCKW
t
20
SCKr
t
20
SCKf
t
40
TXD
t
40
RXS
t
40
RXH
t
30
TRGS
Rev. 3.00 Mar. 14, 2006 Page 769 of 804
Section 21 Electrical Characteristics
Unit
Test Conditions
ns
Figure 21.12
t
Figure 21.13
cyc
t
Scyc
ns
Figure 21.13
ns
Measurement
voltages: V
× 0.7 V
to V
CC
t
Figure 21.13
cyc
t
Scyc
ns
Figure 21.13
ns
Measurement
voltages: V
× 0.7 V
to V
CC
ns
Figure 21.14
ns
ns
ns
Figure 21.15
REJ09B0104-0300
× 0.3 V
CC
× 0.3 V
CC
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