Table of Contents
Advertisement
Figures
Figure 1.1 Block Diagram of H8SX/1527 ...................................................................................... 2
Figure 1.2 Block Diagram of H8SX/1525 ...................................................................................... 3
Figure 1.3 Pin Assignments of H8SX/1527.................................................................................... 4
Figure 1.4 Pin Assignments of H8SX/1525.................................................................................... 5
Figure 2.1 CPU Operating Modes ................................................................................................ 21
Figure 2.2 Exception Vector Table (Normal Mode)..................................................................... 22
Figure 2.3 Stack Structure (Normal Mode) .................................................................................. 22
Figure 2.4 Exception Vector Table (Middle and Advanced Modes) ............................................ 24
Figure 2.5 Stack Structure (Middle and Advanced Modes).......................................................... 25
Figure 2.6 Exception Vector Table (Maximum Modes)............................................................... 26
Figure 2.7 Stack Structure (Maximum Mode) .............................................................................. 26
Figure 2.8 Memory Map............................................................................................................... 27
Figure 2.9 CPU Registers ............................................................................................................. 28
Figure 2.10 Usage of General Registers ....................................................................................... 29
Figure 2.11 Stack .......................................................................................................................... 30
Figure 2.12 General Register Data Formats ................................................................................. 34
Figure 2.13 Memory Data Formats............................................................................................... 35
Figure 2.14 Instruction Formats.................................................................................................... 53
Figure 2.15 Branch Address Specification in Memory Indirect Mode ......................................... 60
Figure 2.16 State Transitions ........................................................................................................ 65
Figure 3.1 Address Map (Advanced Mode) ................................................................................. 72
Figure 4.1 Reset Sequence (On-Chip ROM Enabled Advanced Mode)....................................... 77
Figure 4.2 Stack Status after Exception Handling ........................................................................ 85
Figure 4.3 Operation when SP Value Is Odd................................................................................ 86
Figure 5.1 Block Diagram of Interrupt Controller........................................................................ 88
Figure 5.2 Block Diagram of Interrupts IRQn............................................................................ 104
Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0... 113
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2... 115
Figure 5.5 Interrupt Exception Handling .................................................................................... 116
Figure 5.6 Block Diagram of DMAC and Interrupt Controller .................................................. 118
Figure 5.7 Conflict between Interrupt Generation and Disabling............................................... 122
Rev. 3.00 Mar. 14, 2006 Page xxiii of xxxviii
Downloaded from
Elcodis.com
electronic components distributor
Advertisement
Chapters
Table of Contents
