Renesas H8SX/1520 Series Hardware Manual page 510

Section 13 Controller Area Network (HCAN)
Bit Bit Name
10 IMR2
9 IMR1

8

7 to 5
4 IMR12

3, 2
1 IMR9
0 IMR8
Rev. 3.00 Mar. 14, 2006 Page 472 of 804
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Initial
Value R/W Description
1 R/W
When this bit is cleared to 0, an interrupt request
by IRR2 (OVR0) is enabled. When set to 1, it is
masked.
1 R/W Receive Message Interrupt Mask
When this bit is cleared to 0, an interrupt request
by IRR1 (RM1) is enabled. When set to 1, it is
masked.
0 R
This is a read-only bit and cannot be modified.
All 1 R Reserved
These are read-only bits and cannot be modified.
1 R/W
When this bit is cleared to 0, an interrupt request
by IRR12 (OVR0) is enabled. When set to 1, it is
masked.
All 1 R Reserved
These are read-only bits and cannot be modified.
1 R/W
When this bit is cleared to 0, an interrupt request
by IRR9 (OVR0) is enabled. When set to 1, it is
masked.
1 R/W
When this bit is cleared to 0, an interrupt request
by IRR8 (SLE0) is enabled. When set to 1, it is
masked.
Remote Frame Request Interrupt Mask
Reserved
Bus Operation Interrupt Mask
Unread Interrupt Mask
Mailbox Empty Interrupt Mask