Renesas H8SX/1520 Series Hardware Manual page 30

Figure 17.17 RAM Emulation Flow ........................................................................................... 626
Figure 17.18 Address Map of Overlaid RAM Area ................................................................... 627
Figure 17.19 Programming Tuned Data ..................................................................................... 628
Figure 17.20 Switching between User MAT and User Boot MAT ............................................ 629
Figure 17.21 Boot Program States.............................................................................................. 631
Figure 17.22 Bit-Rate-Adjustment Sequence ............................................................................. 632
Figure 17.23 Communication Protocol Format .......................................................................... 633
Figure 17.24 New Bit-Rate Selection Sequence......................................................................... 644
Figure 17.25 Programming Sequence......................................................................................... 648
Figure 17.26 Erasure Sequence .................................................................................................. 649
Section 18 Clock Pulse Generator
Figure 18.1 Block Diagram of Clock Pulse Generator ............................................................... 661
Figure 18.2 Connection of Crystal Resonator (Example)........................................................... 665
Figure 18.3 Crystal Resonator Equivalent Circuit...................................................................... 665
Figure 18.4 External Clock Input (Examples) ............................................................................ 666
Figure 18.5 Clock Modification Timing..................................................................................... 667
Figure 18.6 Note on Board Design for Oscillation Circuit ......................................................... 668
Figure 18.7 Connection Example of Bypass Capacitor .............................................................. 669
Section 19 Power-Down Modes
Figure 19.1 Mode Transitions..................................................................................................... 672
Figure 19.2 Software Standby Mode Application Example ....................................................... 684
Section 21 Electrical Characteristics
Figure 21.1 Output Load Circuit ................................................................................................ 764
Figure 21.2 System Bus Clock Timing....................................................................................... 765
Figure 21.3 Oscillation Settling Timing after Software Standby Mode ..................................... 766
Figure 21.4 Oscillation Settling Timing ..................................................................................... 766
Figure 21.5 External Input Clock Timing................................................................................... 766
Figure 21.6 Reset Input Timing.................................................................................................. 767
Figure 21.7 Interrupt Input Timing............................................................................................. 768
Figure 21.8 I/O Port Input/Output Timing.................................................................................. 771
Figure 21.9 Data Input Timing for Realtime Input Port ............................................................. 771
Figure 21.10 TPU Input/Output Timing ..................................................................................... 772
Figure 21.11 TPU Clock Input Timing....................................................................................... 772
Figure 21.12 PPG Output Timing............................................................................................... 772
Figure 21.13 SCK Clock Input/Output Timing .......................................................................... 772
Figure 21.14 SCI Input/Output Timing: Clocked Synchronous Mode ....................................... 773
Figure 21.15 A/D Converter External Trigger Input Timing...................................................... 773
Figure 21.16 HCAN Input/Output Timing ................................................................................. 773
Figure 21.17 SSU Timing (Master, CPHS = 1) .......................................................................... 774
Figure 21.18 SSU Timing (Master, CPHS = 0) .......................................................................... 774
Figure 21.19 SSU Timing (Slave, CPHS = 1) ............................................................................ 775
Rev. 3.00 Mar. 14, 2006 Page xxx of xxxviii
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