Renesas H8SX/1520 Series Hardware Manual page 828

Item
Section 15 A/D Converter
15.1 Features
Figure 15.2 Block Diagram of A/D
Converter (Unit 1/AD_1)
15.3.2 A/D Control/Status
Register (ADCSR)
•
Bit 7
15.3.2 A/D Control/Status
Register (ADCSR)
•
Bit 5
Section 16 RAM
Section 17 Flash Memory (0.18-
µm F-ZTAT Version)
17.7.1 Programming/Erasing
Interface Registers
(4) Flash Key Code Register
(FKEY)
Rev. 3.00 Mar. 14, 2006 Page 790 of 804
REJ09B0104-0300
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549 Added
AV 1
CC
10-bit D/A
AV
SS
AN14
AN15
ADTRG1
553 Added
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
553 Amended
In scan mode, A/D conversion continues sequentially
on the specified channels until this bit is cleared to 0 by
software or a reset.
567 Amended
Product Classification
Flash memory version
569 Amended
Programming/erasing time
Programming time: 3 ms (typ) for 128-byte
simultaneous programming, 23.4 µs per byte
Erasing time: 1000 ms (typ) per 1 block (64 kbytes)
Number of programming
The number of programming can be up to 100 times at
the minimum. (1 to 100 times are guaranteed.)
583 Amended
H'5A: Programming/erasing of the flash memory is
enabled. (When FKEY is a value other than
H'5A, the software protection state is entered.)
Control circuit
RAM Size RAM Addresses
H8SX/1527 12 kbytes H'FF9000 to H'FFBFFF
H8SX/1525 12 kbytes H'FF9000 to H'FFBFFF
ADI1 interrupt
signal
Conversion start
trigger from the TPU