Renesas H8SX/1520 Series Hardware Manual page 183

Bit Bit Name
30 DACKE
29 TENDE

28
27 DREQS
26 NRD

25, 24
23 ACT
22 to 20 
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Initial
Value R/W Description
DACK Signal Output Enable
0 R/W
Enables/disables the DACK signal output in single
address mode. This bit is ignored in dual address mode.
0: Enables DACK signal output
1: Disables DACK signal output
TEND Signal Output Enable
0 R/W
Enables/disables the TEND signal output.
0: Enables TEND signal output
1: Disables TEND signal output
0 R/W Reserved
This bit is always read as 0. The write value should
always be 0.
DREQ Select
0 R/W
Selects whether a low level or the falling edge of the
DREQ signal used in external request mode is detected.
When a block transfer is performed in external request
mode, clear this bit to 0 to select the low level detection.
0: Low level detection
1: Falling edge detection (the first transfer after a
0 R/W Next Request Delay
Selects the accepting timing of the next transfer request.
0: Starts accepting the next transfer request after
1: Starts accepting the next transfer request one cycle
All 0 R Reserved
These are read-only bits and cannot be modified.
0 R Active State
Indicates the operating state for the channel.
0: Waiting for a transfer request or a transfer disabled
1: Active state
All 0 R Reserved
These are read-only bits and cannot be modified.
Section 7 DMA Controller (DMAC)
transfer enabled is detected on a low level)
completion of the current transfer
after completion of the current transfer
state by clearing the DTE bit to 0
Rev. 3.00 Mar. 14, 2006 Page 145 of 804
REJ09B0104-0300