Renesas H8SX/1520 Series Hardware Manual page 825

Item
14.3.7 SS Transmit Data
Registers 0 to 3 (SSTDR0 to
SSTDR3)
Table 14.2 Correspondence
Between DATS Bit Setting and
SSTDR
14.3.8 SS Receive Data Registers
0 to 3 (SSRDR0 to SSRDR3)
Table 14.3 Correspondence
Between DATS Bit Setting and
SSRDR
14.4.5 SSU Mode
Figure 14.4 Example of Initial
Settings in SSU Mode
Figure 14.6 Flowchart Example of
Data Transmission (SSU Mode)
Figure 14.8 Flowchart Example of
Data Reception (SSU Mode)
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Page Revision (See Manual for Details)
523 Added
Be sure not to access invalid SSTDRs.
524 Added
524 Added
Be sure not to access invalid SSRDRs
525 Added
530 Amended
[4]
[5]
533 Deleted
[1]
[2]
536 Deleted
[1]
[2]
Start setting initial values
Specify MLS, CPOS, CPHS, CKS2,
CKS1, and CKS0 bits in SSMR
Specify SDOS, SSCKOS, SCSOS,
TENDSTS, SCSATS and SSODTS
bits in SSCR2
Specify TE, RE, TEIE, TIE, RIE,
and CEIE bits in SSER simultaneously
End
Start
Initial setting
TE = 1 (transmission enabled)
Read TDRE in SSSR
Start
Initial setting
RE = 1 (receprion started)
Dummy-read SRDR
Rev. 3.00 Mar. 14, 2006 Page 787 of 804
REJ09B0104-0300