Renesas H8SX/1520 Series Hardware Manual page 834

Item
18.5 Usage Notes
18.5.1 Notes on Clock Pulse
Generator
Section 19 Power-Down Modes
19.2 Register Descriptions
19.2.1 Standby Control Register
(SBYCR)
19.2.3 Module Stop Control
Register C (MSTPCRC)
19.7.4 Software Standby Mode
Application Example
Rev. 3.00 Mar. 14, 2006 Page 796 of 804
REJ09B0104-0300
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667 Deleted
5. When Iφ > Pφ is specified by SCKCR, signals from
the peripheral modules must be synchronized with
the system clock. When CPU instructions are used
to clear the interrupt source flag of a peripheral
module, the flag must be read after being cleared to
0.
673 Amended
to
Bit 15 14

Bit Name SSBY
675
Initial Value 0 1
R/W R/W R/W
Bit 7 6
 
Bit Name
Initial Value 0 0
R/W R/W R/W
Bit Bit Name
15 SSBY

14

13
12 STS4
11 STS3
10 STS2
9 STS1
8 STS0
Added
Initial
Bit Bit Name Value

7 to 0 All 0
678 Amended
Initial
Bit Bit Name Value
1 MSTPC1 0
0 MSTPC0 0
684 Amended
Iφ
13 12 11 10

STS4 STS3 STS2
0 0 1 1
R/W R/W R/W R/W
5 4 3 2
   
0 0 0 0
R/W R/W R/W R/W
Initial
Value R/W
0 R/W
1 R/W
0 R/W
0 R/W
1 R/W
1 R/W
1 R/W
1 R/W
R/W Description
R/W ReservedThese bits are always read as 0. The write
value should always be 0.
R/W Module
R/W On-chip RAM (H'FFF9000 to H'FFFBFFF)
R/W The write value to MSTPC1 and MSTPC0 should
always be the same.
9 8
STS1 STS0
1 1
R/W R/W
1 0
 
0 0
R/W R/W