Renesas H8SX/1520 Series Hardware Manual page 190

Section 7 DMA Controller (DMAC)
Bit Bit Name
26 RPTIE
25 ARS1
24 ARS0

23, 22
21 SAT1
20 SAT0
Rev. 3.00 Mar. 14, 2006 Page 152 of 804
REJ09B0104-0300
Downloaded from Elcodis.com electronic components distributor
Initial
Value R/W Description
0 R/W Repeat Size End Interrupt Enable
Enables/disables a repeat size end interrupt request.
In repeat transfer mode, when the next transfer is
requested after completion of a 1-repeat-size data
transfer while this bit is set to 1, the DTE bit in DMDR is
cleared to 0. At this time, the ESIF bit in DMDR is set to
1 to indicate that a repeat size end interrupt is
requested. Even when the repeat area is not specified
(ARS1 = 1 and ARS0 = 0), a repeat size end interrupt
after a 1-block data transfer can be requested.
In addition, in block transfer mode, when the next
transfer is requested after 1-block data transfer while
this bit is set to 1, the DTE bit in DMDR is cleared to 0.
At this time, the ESIF bit in DMDR is set to 1 to indicate
that a repeat size end interrupt is requested.
0: Disables a repeat size end interrupt
1: Enables a repeat size end interrupt
0 R/W Area Select 1 and 0
0 R/W Specify the block area or repeat area in block or repeat
transfer mode.
00: Specify the block area or repeat area on the source
01: Specify the block area or repeat area on the
10: Do not specify the block area or repeat area
11: Setting prohibited
All 0 R Reserved
These are read-only bits and cannot be modified.
0 R/W Source Address Update Mode 1 and 0
0 R/W Select the update method of the source address
(DSAR). When DSAR is not specified as the transfer
source in single address mode, this bit is ignored.
00: Source address is fixed
01: Source address is updated by adding the offset
10: Source address is updated by adding 1, 2, or 4
11: Source address is updated by subtracting 1, 2, or 4
address
destination address
according to the data access size
according to the data access size