Table of Contents
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Section 2 CPU
Classifi-
cation
Instruction
Bit
BFLD
manipu-
BFST
lation
Branch
BRA/BS,
BRA/BC*
BSR/BS,
BSR/BC*
System
LDC (CCR, EXR)
control
LDC (VBR, SBR)
STC (CCR, EXR)
STC (VBR, SBR)
ANDC, ORC,
XORC
SLEEP
NOP
[Legend]
d:
d:16 or d:32
S:
Can be specified as a source operand.
D:
Can be specified as a destination operand.
SD:
Can be specified as either a source or destination operand or both.
S/D:
Can be specified as either a source or destination operand.
S:4:
4-bit immediate data can be specified as a source operand.
Notes: 1. Only @aa:16 is available.
2. @ERn+ as a source operand and @−ERn as a destination operand
3. Specified by ER5 as a source address and ER6 as a destination address for data
transfer.
4. Size of data to be added with a displacement
5. Only @ERn− is available
6. When the number of bits to be shifted is 1, 2, 4, 8, or 16
7. When the number of bits to be shifted is specified by 5-bit immediate data or a general
register
8. Size of data to specify a branch condition
9. Byte when immediate or register direct, otherwise, word
10. Only @ERn+ is available
11. Only @−ERn is available
12. Not available in this LSI.
Rev. 3.00 Mar. 14, 2006 Page 40 of 804
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Size
#xx
B
B
B
8
B
8
9
B/W*
S
L
9
B/W*
L
B
S
Addressing Mode
@(d,
RnL.B/
Rn.W/
Rn
@ERn
@(d,ERn)
ERn.L)
D
S
S
D
S
S
S
S
S
S
D
D
D
D
@−ERn/
@ERn+/
@ERn−/
@aa:16/
@+ERn
@aa:8
@aa:32
S
S
D
D
S
S
S
S
10
S*
S
11
D*
D
O
O
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