Renesas H8SX/1520 Series Hardware Manual page 11

4.6 Interrupts.............................................................................................................................. 81
4.6.1
4.6.2
4.7 Instruction Exception Handling ........................................................................................... 83
4.7.1
4.7.2
4.8 Stack Status after Exception Handling................................................................................. 85
4.9 Usage Note........................................................................................................................... 86
Section 5 Interrupt Controller ..............................................................................87
5.1 Features................................................................................................................................ 87
5.2 Input/Output Pins ................................................................................................................. 88
5.3 Register Descriptions ........................................................................................................... 89
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.4 Interrupt Sources................................................................................................................ 103
5.4.1
5.4.2
5.5 Interrupt Exception Handling Vector Table....................................................................... 105
5.6 Interrupt Control Modes and Interrupt Operation .............................................................. 112
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.7 CPU Priority Control Function Over DMAC .................................................................... 120
5.8 Usage Notes ....................................................................................................................... 122
5.8.1
5.8.2
5.8.3
5.8.4
5.8.5
5.8.6
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Interrupt Sources..................................................................................................... 81
Interrupt Exception Handling ................................................................................. 82
Trap Instruction....................................................................................................... 83
Exception Handling by Illegal Instruction .............................................................. 84
Interrupt Control Register (INTCR) ....................................................................... 89
CPU Priority Control Register (CPUPCR) ............................................................. 90
Interrupt Priority Registers A to G, I, K to O, Q, and R
(IPRA to IPRG, IPRI, IPRK to IPRO, IPRQ, and IPRR) ....................................... 92
IRQ Enable Register (IER) ..................................................................................... 94
IRQ Sense Control Registers H and L (ISCRH and ISCRL) .................................. 96
IRQ Status Register (ISR)..................................................................................... 101
Software Standby Release IRQ Enable Register (SSIER) .................................... 102
External Interrupts ................................................................................................ 103
Internal Interrupts ................................................................................................. 104
Interrupt Control Mode 0 ...................................................................................... 112
Interrupt Control Mode 2 ...................................................................................... 114
Interrupt Exception Handling Sequence ............................................................... 116
Interrupt Response Times ..................................................................................... 117
DMAC Activation by Interrupt............................................................................. 118
Conflict between Interrupt Generation and Disabling .......................................... 122
Instructions that Disable Interrupts ....................................................................... 123
Times when Interrupts are Disabled ..................................................................... 123
Interrupts during Execution of EEPMOV Instruction........................................... 123
Interrupts during Execution of MOVMD and MOVSD Instructions.................... 123
Interrupt Flags of Peripheral Modules .................................................................. 124
Rev. 3.00 Mar. 14, 2006 Page xi of xxxviii