Renesas H8SX/1520 Series Hardware Manual page 507

Bit Bit Name

3, 2
1 IRR9
0 IRR8
Note: Only 1 can be written to clear the flag.
*
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Initial
Value R/W

All 0
0 R
0 R/(W)*
Section 13 Controller Area Network (HCAN)
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Unread Interrupt Flag
Status flag indicating that a receive message has
been overwritten before being read.
[Setting condition]
When UMSR (unread message status register) is
set
[Clearing condition]
Clearing of all bits in UMSR (unread message
status register)
Mailbox Empty Interrupt Flag
Status flag indicating that the next transmit
message can be stored in the mailbox.
[Setting condition]
•
When TXPR (transmit wait register) is cleared
by completion of transmission or completion
of transmission abort
[Clearing condition]
•
Writing 1
(When the CPU is used to clear this flag by
writing 1 while the corresponding interrupt is
enabled, be sure to read the flag after writing
1 to it.)
Rev. 3.00 Mar. 14, 2006 Page 469 of 804
REJ09B0104-0300