Renesas H8SX/1520 Series Hardware Manual page 833

Item
17.13 Standard Serial
Communication Interface
Specifications for Boot Mode
(4) Receive Data Check
(8) Programming/Erasing State
17.14 Usage Notes
Section 18 Clock Pulse Generator
18.1 Register Description
18.1.1 System Clock Control
Register (SCKCR)
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Page Revision (See Manual for Details)
643 Deleted
3. Operating frequency error
647 Amended
Command Command Name
H'4C User boot MAT blank check
H'4D User MAT blank check
H'4C User boot MAT blank check
H'4D User MAT blank check
H'4F Boot program status inquiry
658, Added
659
10. To program the flash memory, the program data
and program must be allocated to addresses
which are higher than those of the external
interrupt vector table and H'FF must be written to
all the system reserved areas in the exception
handling vector table.
15. The contents of some general registers are not
saved in a programming/ programming
end/erasing program. When needed, save general
registers in the procedure program.
662 Amended
SCKCR controls Bφ clock output and frequencies of the
system, peripheral module, and external clocks, and
selects the Bφ clock to be output.
Bit Bit Name
15 PSTOP1
Description
Checks the blank data of the user boot MAT
Checks the blank data of the user MAT
Checks whether the contents of the user boot
MAT are blank
Checks whether the contents of the user MAT
are blank
Inquires into the boot program's status
Description
Bφ Clock Output Enable
Controls Bφ output on PA7.
•
Normal operation
0: Bφ output
1: Fixed high
•
Software standby mode
X: Fixed high
•
Hardware standby mode
X: Hi-Z
Rev. 3.00 Mar. 14, 2006 Page 795 of 804
REJ09B0104-0300