Renesas H8SX/1520 Series Hardware Manual page 13

7.4.11 Bus Cycles in Single Address Mode..................................................................... 191
7.5 DMA Transfer End ............................................................................................................ 196
7.6 Relationship among DMAC and Other Bus Masters ......................................................... 198
7.6.1
7.6.2
7.7 Interrupt Sources................................................................................................................ 200
7.8 Notes on Usage .................................................................................................................. 203
Section 8 I/O Ports .............................................................................................205
8.1 Register Descriptions ......................................................................................................... 210
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.1.7
8.2 Output Buffer Control........................................................................................................ 216
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.3 Port Function Controller .................................................................................................... 243
8.3.1
8.3.2
8.3.3
8.4 Usage Notes ....................................................................................................................... 249
8.4.1
8.4.2
Section 9 16-Bit Timer Pulse Unit (TPU) .........................................................251
9.1 Features.............................................................................................................................. 251
9.2 Input/Output Pins ............................................................................................................... 258
9.3 Register Descriptions ......................................................................................................... 260
9.3.1
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CPU Priority Control Function Over DMAC ....................................................... 198
Bus Arbitration among DMAC and Other Bus Masters ....................................... 199
Data Direction Register (PnDDR) (n = 1 to 3, 6, A, D, H, J, and K).................... 212
Data Register (PnDR) (n = 1 to 3, 6, A, D, H, J, and K)....................................... 212
Port Register (PORTn) (n = 1 to 6, A, D, H, J, and K) ......................................... 213
Input Buffer Control Register (PnICR) (n = 1 to 6, A, D, H, J, and K) ................ 213
Pull-Up MOS Control Register (PnPCR) (n = D, H, J, and K)............................. 214
Open-Drain Control Register (PnODR) (n = 2).................................................... 215
Port H Realtime Input Data Register (PHRTIDR)................................................ 215
Port 1..................................................................................................................... 216
Port 2..................................................................................................................... 219
Port 3..................................................................................................................... 221
Port 6..................................................................................................................... 225
Port A.................................................................................................................... 227
Port D.................................................................................................................... 230
Port H.................................................................................................................... 233
Port J ..................................................................................................................... 233
Port K.................................................................................................................... 236
Port Function Control Register 9 (PFCR9)........................................................... 243
Port Function Control Register A (PFCRA) ......................................................... 245
Port Function Control Register B (PFCRB).......................................................... 247
Notes on Input Buffer Control Register (ICR) Setting ......................................... 249
Notes on Port Function Control Register (PFCR) Settings................................... 249
Timer Control Register (TCR).............................................................................. 265
Rev. 3.00 Mar. 14, 2006 Page xiii of xxxviii