Renesas H8SX/1520 Series Hardware Manual page 390

Section 10 Programmable Pulse Generator (PPG)
• NDRL
If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the
same address and can be accessed at one time, as shown below.
Bit Bit Name
7 NDR7
6 NDR6
5 NDR5
4 NDR4
3 NDR3
2 NDR2
1 NDR1
0 NDR0
If pulse output groups 0 and 1 have different output triggers, the upper four bits and lower four
bits are mapped to different addresses as shown below.
Bit Bit Name
7 NDR7
6 NDR6
5 NDR5
4 NDR4

3 to 0
Bit Bit Name

7 to 4
3 NDR3
2 NDR2
1 NDR1
0 NDR0
Rev. 3.00 Mar. 14, 2006 Page 352 of 804
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Initial
Value R/W Description
0 R/W Next Data Register 7 to 0
0 R/W The register contents are transferred to the
corresponding PODRL bits by the output trigger specified
0 R/W
with PCR.
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Initial
Value R/W Description
0 R/W Next Data Register 7 to 4
0 R/W The register contents are transferred to the
corresponding PODRL bits by the output trigger specified
0 R/W
with PCR.
0 R/W
All 1 R Reserved
These are read-only bits and cannot be modified.
Initial
Value R/W Description
All 1 R Reserved
These are read-only bits and cannot be modified.
0 R/W Next Data Register 3 to 0
0 R/W The register contents are transferred to the
corresponding PODRL bits by the output trigger specified
0 R/W
with PCR.
0 R/W