Renesas H8SX/1520 Series Hardware Manual page 824

Item
Section 11 Watchdog Timer
(WDT)
11.2.2 Timer Control/Status
Register (TCSR)
•
Bit 7
Section 12 Serial Communication
Interface (SCI)
12.3.7 Serial Status Register
(SSR)
Bit Functions in Normal Serial
Communication Interface Mode
(When SMIF in SCMR = 0):
•
Bit 7 to 3
Bit Functions in Smart Card
Interface Mode (When SMIF in
SCMR = 1):
•
Bit 7 to 3
12.4.2 Receive Data Sampling
Timing and Reception Margin in
Asynchronous Mode
12.9.6 Restrictions on Using
DMAC
Section 13 Controller Area
Network (HCAN)
13.3.2 General Status Register
(GSR)
•
Bit 2
13.3.11 Interrupt Register (IRR)
•
Bit 15 to 11, 8, 4, 0
14.3.5 SS Status Register (SSSR)
•
Bit 6, 3 to 0
Rev. 3.00 Mar. 14, 2006 Page 786 of 804
REJ09B0104-0300
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Page Revision (See Manual for Details)
370 Added
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
390 Added
to
(When the CPU is used to clear this flag by writing 0
392
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
393 Added
to
(When the CPU is used to clear this flag by writing 0
395
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
Amended
407
1
M = (0.5 – |
2N
443 Amended
...and wait for at least five Pφ clock cycles before...
456 Amended
[Setting condition]
•
Start of message transmission (SOF)
[Clearing condition]
•
Third bit of Intermission after EOF (End of Frame)
465 Amended
to
(When the CPU is used to clear this flag by writing 0
469
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
519 Amended
to
(When the CPU is used to clear this flag by writing 0
521
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
| D – 0.5 |
) – (L – 0.5) F –
N
(1 + F ) | × 100[%]