Renesas H8SX/1520 Series Hardware Manual page 430

Section 12 Serial Communication Interface (SCI)
Bit Bit Name
3 PER
2 TEND
1 MPB
0 MPBT
Note: * Only 0 can be written, to clear the flag.
Rev. 3.00 Mar. 14, 2006 Page 392 of 804
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Initial
Value R/W Description
0 R/(W)* Parity Error
Indicates that a parity error has occurred during reception
in asynchronous mode and the reception ends
abnormally.
[Setting condition]
•
[Clearing condition]
•
1 R Transmit End
[Setting conditions]
•
•
[Clearing conditions]
•
•
0 R Multiprocessor Bit
Stores the multiprocessor bit value in the receive frame.
When the RE bit in SCR is cleared to 0 its previous state
is retained.
0 R/W Multiprocessor Bit Transfer
Sets the multiprocessor bit value to be added to the
transmit frame.
When a parity error is detected during reception
Receive data when the parity error occurs is
transferred to RDR, however, the RDRF flag is not
set. Note that when the PER flag is being set to 1, the
subsequent serial reception cannot be performed. In
clocked synchronous mode, serial transmission also
cannot continue.
When 0 is written to PER after reading PER = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
Even when the RE bit in SCR is cleared, the PER bit
is not affected and retains its previous value.
When the TE bit in SCR is 0
When TDRE = 1 at transmission of the last bit of a
transmit character
When 0 is written to TDRE after reading TDRE = 1
When a TXI interrupt request is issued allowing
DMAC to write data to TDR