Renesas H8SX/1520 Series Hardware Manual page 35

Table 9.15
Table 9.16
Table 9.17
Table 9.18
Table 9.19
Table 9.20
Table 9.21
Table 9.22
Table 9.23
Table 9.24
Table 9.25
Table 9.26
Table 9.27
Table 9.28
Table 9.29
Table 9.30
Table 9.31
Table 9.32
Table 9.33
Table 9.34
Table 9.35
Table 9.36
Table 9.37
Table 9.38
Table 9.39
Section 10 Programmable Pulse Generator (PPG)
Table 10.1
Section 11 Watchdog Timer (WDT)
Table 11.1
Section 12 Serial Communication Interface (SCI)
Table 12.1
Table 12.2
Table 12.3
Table 12.3
Table 12.4
Table 12.5
Table 12.6
Table 12.7
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TIORH_0 .............................................................................................................. 274
TIORL_0............................................................................................................... 275
TIOR_1 ................................................................................................................. 276
TIOR_2 ................................................................................................................. 277
TIORH_3 .............................................................................................................. 278
TIORL_3............................................................................................................... 279
TIOR_4 ................................................................................................................. 280
TIOR_5 ................................................................................................................. 281
TIORH_0 .............................................................................................................. 282
TIORL_0............................................................................................................... 283
TIOR_1 ................................................................................................................. 284
TIOR_2 ................................................................................................................. 285
TIORH_3 .............................................................................................................. 286
TIORL_3............................................................................................................... 287
TIOR_4 ................................................................................................................. 288
TIOR_5 ................................................................................................................. 289
Register Combinations in Buffer Operation ......................................................... 307
Cascaded Combinations........................................................................................ 311
PWM Output Registers and Output Pins .............................................................. 314
Clock Input Pins in Phase Counting Mode ........................................................... 318
Up/Down-Count Conditions in Phase Counting Mode 1...................................... 320
Up/Down-Count Conditions in Phase Counting Mode 2...................................... 321
Up/Down-Count Conditions in Phase Counting Mode 3..................................... 322
Up/Down-Count Conditions in Phase Counting Mode 4...................................... 323
TPU Interrupts ...................................................................................................... 326
Pin Configuration.................................................................................................. 346
WDT Interrupt Source .......................................................................................... 373
Pin Configuration.................................................................................................. 379
Relationships between N Setting in BRR and Bit Rate B..................................... 398
Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 399
Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 400
Maximum Bit Rate for Each Operating Frequency (Asynchronous Mode).......... 401
Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................ 401
BRR Settings for Various Bit Rates (Clocked Synchronous Mode)..................... 402
Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) .... 403
Rev. 3.00 Mar. 14, 2006 Page xxxv of xxxviii