Renesas H8SX/1520 Series Hardware Manual page 534

Section 13 Controller Area Network (HCAN)
(3)
Message reception
When a message is received, a CRC check is performed automatically. If the result of the CRC
check is normal, ACK is transmitted in the ACK field irrespective of whether the message can be
received or not.
• Data frame reception
If the received message is confirmed to be error-free by the CRC check, the identifier in the
mailbox (and also LAFM in the case of mailbox 0 only) and the identifier of the receive
message are compared. If a complete match is found, the message is stored in the matching
mailbox. The message identifier comparison is carried out on each mailbox in turn, starting
with mailbox 0 and ending with mailbox 15. If a complete match is found, the comparison
ends at that point, the message is stored in the matching mailbox, and the corresponding
receive complete bit (RXPR0 to RXPR15) in the receive complete register (RXPR) is set.
However, if the identifier matches that of mailbox 0 LAFM, the mailbox comparison sequence
does not end at that point, but continues from mailbox 1. Therefore, the message for mailbox 0
can also be received by another mailbox. Note that the same message cannot be stored in two
or more mailbox of the mailboxes 1 to 15. On receiving a message, a CPU interrupt request
may be generated according to the settings of the mailbox interrupt mask register (MBIMR)
and interrupt mask register (IMR).
• Remote frame reception
A mailbox can store two kinds of messages: data frames and remote frames. A remote frame
differs from a data frame in the value of the remote transmission request bit (RTR) in the
message control register and its 0-byte data field. The data length to be returned in a data frame
must be stored in the data length code (DLC) in the message control.
When a remote frame (RTR = recessive) is received, the corresponding bit in the remote
request wait register (RFPR) is set. Interrupts can be sent to the CPU according to the settings
of the corresponding bit (MBIMR0 to MBIMR15) in the mailbox interrupt mask register
(MBIMR) and the remote frame request interrupt mask (IRR2) in the interrupt mask register
(IMR).
Rev. 3.00 Mar. 14, 2006 Page 496 of 804
REJ09B0104-0300
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