Renesas H8SX/1520 Series Hardware Manual page 25

Figure 7.31 Example of Transfer in Block Transfer Mode Activated
Figure 7.32 Example of Transfer in Normal Transfer Mode Activated
Figure 7.33 Example of Transfer in Single Address Mode (Byte Read) .................................... 191
Figure 7.34 Example of Transfer in Single Address Mode (Byte Write) .................................... 192
Figure 7.35 Example of Transfer in Single Address Mode Activated
Figure 7.36 Example of Transfer in Single Address Mode Activated
Figure 7.37 Example of Transfer in Single Address Mode Activated
Figure 7.38 Interrupt and Interrupt Sources................................................................................ 202
Figure 7.39 Procedure Example of Resuming Transfer by Clearing Interrupt Source ............... 202
Section 8 I/O Ports
Figure 8.1 Port Block Diagram................................................................................................... 211
Section 9 16-Bit Timer Pulse Unit (TPU)
Figure 9.1 Block Diagram of TPU (Unit 0)................................................................................ 256
Figure 9.2 Block Diagram of TPU (Unit 1)................................................................................ 257
Figure 9.3 Example of Counter Operation Setting Procedure .................................................... 299
Figure 9.4 Free-Running Counter Operation .............................................................................. 300
Figure 9.5 Periodic Counter Operation....................................................................................... 301
Figure 9.6 Example of Setting Procedure for Waveform Output by Compare Match................ 301
Figure 9.7 Example of 0-Output/1-Output Operation................................................................. 302
Figure 9.8 Example of Toggle Output Operation ....................................................................... 302
Figure 9.9 Example of Setting Procedure for Input Capture Operation...................................... 303
Figure 9.10 Example of Input Capture Operation....................................................................... 304
Figure 9.11 Example of Synchronous Operation Setting Procedure .......................................... 305
Figure 9.12 Example of Synchronous Operation........................................................................ 306
Figure 9.13 Compare Match Buffer Operation........................................................................... 307
Figure 9.14 Input Capture Buffer Operation............................................................................... 308
Figure 9.15 Example of Buffer Operation Setting Procedure..................................................... 308
Figure 9.16 Example of Buffer Operation (1)............................................................................. 309
Figure 9.17 Example of Buffer Operation (2)............................................................................. 310
Figure 9.18 Example of Cascaded Operation Setting Procedure ................................................ 311
Figure 9.19 Example of Cascaded Operation (1)........................................................................ 312
Figure 9.20 Example of Cascaded Operation (2)........................................................................ 312
Figure 9.21 Example of PWM Mode Setting Procedure ............................................................ 315
Figure 9.22 Example of PWM Mode Operation (1) ................................................................... 316
Figure 9.23 Example of PWM Mode Operation (2) ................................................................... 316
Figure 9.24 Example of PWM Mode Operation (3) ................................................................... 317
Figure 9.25 Example of Phase Counting Mode Setting Procedure............................................. 319
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by DREQ Low Level .............................................................................................. 189
by DREQ Low Level with NRD = 1....................................................................... 190
by DREQ Falling Edge ........................................................................................... 193
by DREQ Low Level .............................................................................................. 194
by DREQ Low Level with NRD = 1....................................................................... 195
Rev. 3.00 Mar. 14, 2006 Page xxv of xxxviii