Renesas H8SX/1520 Series Hardware Manual page 184

Section 7 DMA Controller (DMAC)
Bit Bit Name
19 ERRF

18
17 ESIF
Rev. 3.00 Mar. 14, 2006 Page 146 of 804
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Initial
Value R/W Description
0 R/(W)* System Error Flag
Indicates that an address error or an NMI interrupt has
been generated. This bit is available only in DMDR_0.
Setting this bit to 1 prohibits writing to the DTE bit for all
the channels. This bit is reserved in DMDR_1 to
DMDR_3. It is always read as 0 and cannot be modified.
0: An address error or an NMI interrupt has not been
1: An address error or an NMI interrupt has been
[Clearing condition]
•
[Setting condition]
•
However, when an address error or an NMI interrupt has
been generated in module stop mode, this bit is not set.
0 R Reserved
This is a read-only bit and cannot be modified.
0 R/(W)* Transfer Escape Interrupt Flag
Indicates that a transfer escape end interrupt has been
requested. A transfer escape end means that a transfer
is terminated before the transfer counter reaches 0.
0: A transfer escape end interrupt has not been
1: A transfer escape end interrupt has been requested
[Clearing conditions]
•
•
[Setting conditions]
•
•
•
generated
generated
When clearing to 0 after reading ERRF = 1
When an address error or an NMI interrupt has been
generated
requested
When setting the DTE bit to 1
When clearing to 0 before reading ESIF = 1
When a transfer size error interrupt is requested
When a repeat size end interrupt is requested
When a transfer end interrupt by an extended repeat
area overflow is requested