Renesas H8SX/1520 Series Hardware Manual page 24

Section 6 Bus Controller (BSC)
Figure 6.1 Block Diagram of Bus Controller.............................................................................. 125
Figure 6.2 Internal Bus Configuration........................................................................................ 127
Figure 6.3 Example of Timing when Write Data Buffer Function is Used ................................ 130
Section 7 DMA Controller (DMAC)
Figure 7.1 Block Diagram of DMAC ......................................................................................... 135
Figure 7.2 Example of Signal Timing in Dual Address Mode ................................................... 159
Figure 7.3 Operations in Dual Address Mode ............................................................................ 159
Figure 7.4 Data Flow in Single Address Mode........................................................................... 160
Figure 7.5 Example of Signal Timing in Single Address Mode ................................................. 161
Figure 7.6 Operations in Single Address Mode.......................................................................... 161
Figure 7.7 Example of Signal Timing in Normal Transfer Mode............................................... 162
Figure 7.8 Operations in Normal Transfer Mode ....................................................................... 162
Figure 7.9 Operations in Repeat Transfer Mode ........................................................................ 163
Figure 7.10 Operations in Block Transfer Mode ........................................................................ 164
Figure 7.11 Operation in Single Address Mode in Block Transfer Mode
(Block Area Specified) ........................................................................................... 165
Figure 7.12 Operation in Dual Address Mode in Block Transfer Mode
(Block Area Not Specified) ..................................................................................... 165
Figure 7.13 Example of Timing in Cycle Stealing Mode ........................................................... 169
Figure 7.14 Example of Timing in Burst Mode.......................................................................... 169
Figure 7.15 Example of Extended Repeat Area Operation......................................................... 171
Figure 7.16 Example of Extended Repeat Area Function in Block Transfer Mode ................... 171
Figure 7.17 Address Update Method.......................................................................................... 172
Figure 7.18 Operation of Offset Addition .................................................................................. 173
Figure 7.19 XY Conversion Operation Using Offset Addition in Repeat Transfer Mode.......... 174
Figure 7.20 XY Conversion Flowchart Using Offset Addition in Repeat Transfer Mode ......... 175
Figure 7.21 Procedure for Changing Register Setting For Channel being Transferred .............. 179
Figure 7.22 Example of Timing for Channel Priority................................................................. 181
Figure 7.23 Example of Bus Timing of DMA Transfer ............................................................. 182
Figure 7.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing......................... 183
Figure 7.25 Example of Transfer in Normal Transfer Mode by Cycle Stealing
(Transfer Source DSAR = Odd Address and Source Address Increment).............. 184
Figure 7.26 Example of Transfer in Normal Transfer Mode by Cycle Stealing
(Transfer Destination DDAR = Odd Address and Destination
Figure 7.27 Example of Transfer in Normal Transfer Mode by Burst Access ........................... 185
Figure 7.28 Example of Transfer in Block Transfer Mode......................................................... 186
Figure 7.29 Example of Transfer in Normal Transfer Mode Activated
by DREQ Falling Edge ........................................................................................... 187
Figure 7.30 Example of Transfer in Normal Transfer Mode Activated
by DREQ Low Level .............................................................................................. 188
Rev. 3.00 Mar. 14, 2006 Page xxiv of xxxviii
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Address Decrement) .............................................................................................. 184