Renesas H8SX/1520 Series Hardware Manual page 841

SYSCR ......................... 69, 706, 732, 755
TCNT......................... 296, 368, 708, 709,
................................... 735, 736, 757, 758
TCR ............................ 265, 709, 736, 758
TCSR .......................... 369, 708, 735, 757
TDR ............................ 381, 706, 733, 755
TEC............................. 473, 688, 712, 738
TGR ............................ 296, 709, 736, 758
TIER ........................... 290, 709, 736, 758
TIOR........................... 272, 709, 736, 758
TMDR......................... 270, 709, 736, 758
TSR......................292, 382, 709, 736, 758
TSTR .......................... 297, 709, 736, 757
TSYR.......................... 298, 709, 736, 757
TXACK ...................... 461, 688, 711, 738
TXCR ......................... 460, 688, 711, 738
TXPR.......................... 459, 688, 711, 738
UMSR......................... 474, 688, 712, 738
VBR...................................................... 32
Remote frame reception.......................... 496
Repeat transfer mode .............................. 163
Reset ......................................................... 76
Reset exception handling.......................... 76
Reset state ................................................. 64
Resolution............................................... 561
S
Sample-and-hold circuit.......................... 559
Scan mode .............................................. 557
Serial communication interface (SCI) .... 377
Single address mode ............................... 160
Single mode ............................................ 556
Sleep mode ............................. 671, 672, 680
Slot illegal instruction............................... 84
Smart card interface................................ 429
Software protection................................. 624
Software standby mode........... 671, 672, 681
SSU mode ............................................... 530
Stack status after exception handling........ 85
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Standard serial communication
interface specifications for boot mode .... 630
Start bit.................................................... 405
State transitions......................................... 65
Stop bit.................................................... 405
Synchronous clearing.............................. 305
Synchronous presetting ........................... 305
Synchronous serial communication
unit (SSU) ............................................... 509
System clock (Iφ) ............................ 128, 661
T
Time quanta (tq)...................................... 487
Toggle output.......................................... 302
Trace exception handling .......................... 78
Transfer clock ......................................... 526
Transmit/receive data.............................. 405
Trap instruction exception handling.......... 83
U
Unread message overwrite ...................... 497
User boot MAT ....................................... 629
User boot mode ....................................... 613
User MAT ............................................... 629
User program mode................................. 603
V
Vector table address.................................. 74
Vector table address offset........................ 74
W
Watchdog timer (WDT) .......................... 367
Watchdog timer mode............................. 372
Write data buffer function....................... 130
Rev. 3.00 Mar. 14, 2006 Page 803 of 804
REJ09B0104-0300