Renesas H8SX/1520 Series Hardware Manual page 29

Figure 14.12 Example of Initial Settings in Clock Synchronous Communication Mode ........... 539
Figure 14.13 Example of Transmission Operation
Figure 14.14 Flowchart Example of Transmission Operation
Figure 14.15 Example of Reception Operation
Figure 14.16 Flowchart Example of Data Reception
Figure 14.17 Flowchart Example of Simultaneous Transmission/Reception
Section 15 A/D Converter
Figure 15.1 Block Diagram of A/D Converter (Unit 0/AD_0) ................................................... 548
Figure 15.2 Block Diagram of A/D Converter (Unit 1/AD_1) ................................................... 549
Figure 15.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) ............ 557
Figure 15.4 Example of A/D Conversion
Figure 15.5 A/D Conversion Timing .......................................................................................... 559
Figure 15.6 External Trigger Input Timing ................................................................................ 560
Figure 15.7 A/D Conversion Accuracy Definitions.................................................................... 562
Figure 15.8 A/D Conversion Accuracy Definitions.................................................................... 562
Figure 15.9 Example of Analog Input Circuit ............................................................................ 563
Figure 15.10 Example of Analog Input Protection Circuit ......................................................... 565
Figure 15.11 Analog Input Pin Equivalent Circuit ..................................................................... 566
Section 17 Flash Memory (0.18-mm F-ZTAT Version)
Figure 17.1 Block Diagram of Flash Memory............................................................................ 570
Figure 17.2 Mode Transition of Flash Memory.......................................................................... 571
Figure 17.3 Memory MAT Configuration .................................................................................. 573
Figure 17.4 Block Structure of User MAT ................................................................................. 574
Figure 17.5 Procedure for Creating Procedure Program............................................................. 575
Figure 17.6 System Configuration in Boot Mode....................................................................... 599
Figure 17.7 Automatic-Bit-Rate Adjustment Operation............................................................. 600
Figure 17.8 Boot Mode State Transition Diagram...................................................................... 601
Figure 17.9 Programming/Erasing Flow..................................................................................... 603
Figure 17.10 RAM Map when Programming/Erasing is Executed ............................................ 604
Figure 17.11 Programming Procedure in User Program Mode .................................................. 605
Figure 17.12 Erasing Procedure in User Program Mode ............................................................ 610
Figure 17.13 Repeating Procedure of Erasing, Programming,
Figure 17.14 Procedure for Programming User MAT in User Boot Mode ................................ 614
Figure 17.15 Procedure for Erasing User MAT in User Boot Mode .......................................... 616
Figure 17.16 Transitions to Error Protection State ..................................................................... 625
Downloaded from Elcodis.com electronic components distributor
(Clock Synchronous Communication Mode)........................................................ 540
(Clock Synchronous Communication Mode)........................................................ 541
(Clock Synchronous Communication Mode)........................................................ 542
(Clock Synchronous Communication Mode)........................................................ 543
(Clock Synchronous Communication Mode)........................................................ 544
(Scan Mode, Three Channels (AN0 to AN2) Selected) .......................................... 558
and RAM Emulation in User Program Mode ....................................................... 612
Rev. 3.00 Mar. 14, 2006 Page xxix of xxxviii