Renesas H8SX/1520 Series Hardware Manual page 425

Bit Bit Name
3 MPIE
2 TEIE
1 CKE1
0 CKE0
Note: X: Don't care
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Initial
Value R/W Description
0 R/W Multiprocessor Interrupt Enable (valid only when the MP
bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and ORER status flags in SSR is disabled.
On receiving data in which the multiprocessor bit is 1, this
bit is automatically cleared and normal reception is
resumed. For details, see section 12.5, Multiprocessor
Communication Function.
When receive data including MPB = 0 in SSR is being
received, transfer of the received data from RSR to RDR,
detection of reception errors, and the settings of RDRF,
FER, and ORER flags in SSR are not performed. When
receive data including MPB = 1 is received, the MPB bit
in SSR is set to 1, the MPIE bit is automatically cleared to
0, and RXI and ERI interrupt requests (in the case where
the TIE and RIE bits in SCR are set to 1) and setting of
the FER and ORER flags are enabled.
0 R/W Transmit End Interrupt Enable
When this bit is set to 1, a TEI interrupt request is
enabled. A TEI interrupt request can be cancelled by
reading 1 from the TDRE flag and then clearing the flag
to 0 in order to clear the TEND flag to 0, or by clearing
the TEIE bit to 0.
0 R/W Clock Enable 1, 0
0 R/W These bits select the clock source and SCK pin function.
•
00: On-chip baud rate generator
01: On-chip baud rate generator
1X: External clock
•
0X: Internal clock
1X: External clock
Section 12 Serial Communication Interface (SCI)
Asynchronous mode
(SCK pin functions as I/O port.)
(Outputs a clock with the same frequency as the bit
rate from the SCK pin.)
(Inputs a clock with a frequency 16 times the bit rate
from the SCK pin.)
Clocked synchronous mode
(SCK pin functions as clock output.)
(SCK pin functions as clock input.)
Rev. 3.00 Mar. 14, 2006 Page 387 of 804
REJ09B0104-0300