Renesas H8SX/1520 Series Hardware Manual page 15

10.3 Register Descriptions ......................................................................................................... 347
10.3.1 Next Data Enable Registers H, L (NDERH, NDERL) ......................................... 347
10.3.2 Output Data Registers H, L (PODRH, PODRL)................................................... 349
10.3.3 Next Data Registers H, L (NDRH, NDRL) .......................................................... 350
10.3.4 PPG Output Control Register (PCR) .................................................................... 353
10.3.5 PPG Output Mode Register (PMR) ...................................................................... 354
10.4 Operation ........................................................................................................................... 356
10.4.1 Output Timing....................................................................................................... 356
10.4.2 Sample Setup Procedure for Normal Pulse Output............................................... 357
10.4.3 Example of Normal Pulse Output (Example of 5-Phase Pulse Output)................ 358
10.4.4 Non-Overlapping Pulse Output............................................................................. 359
10.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output ............................... 361
10.4.6 Example of Non-Overlapping Pulse Output
10.4.7 Inverted Pulse Output ........................................................................................... 364
10.4.8 Pulse Output Triggered by Input Capture ............................................................. 365
10.5 Usage Notes ....................................................................................................................... 365
10.5.1 Module Stop Mode Setting ................................................................................... 365
10.5.2 Operation of Pulse Output Pins............................................................................. 365
Section 11 Watchdog Timer (WDT)..................................................................367
11.1 Features.............................................................................................................................. 367
11.2 Register Descriptions ......................................................................................................... 368
11.2.1 Timer Counter (TCNT)......................................................................................... 368
11.2.2 Timer Control/Status Register (TCSR)................................................................. 369
11.2.3 Reset Control/Status Register (RSTCSR)............................................................. 370
11.3 Operation ........................................................................................................................... 372
11.3.1 Watchdog Timer Mode ......................................................................................... 372
11.3.2 Interval Timer Mode............................................................................................. 373
11.4 Interrupt Source ................................................................................................................. 373
11.5 Usage Notes ....................................................................................................................... 374
11.5.1 Notes on Register Access...................................................................................... 374
11.5.2 Conflict between Timer Counter (TCNT) Write and Increment........................... 375
11.5.3 Changing Values of Bits CKS2 to CKS0.............................................................. 375
11.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode................. 375
11.5.5 Transition to Watchdog Timer Mode or Software Standby Mode........................ 376
Section 12 Serial Communication Interface (SCI) ............................................377
12.1 Features.............................................................................................................................. 377
12.2 Input/Output Pins ............................................................................................................... 379
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(Example of 4-Phase Complementary Non-Overlapping Pulse Output) .............. 362
Rev. 3.00 Mar. 14, 2006 Page xv of xxxviii