Renesas H8SX/1520 Series Hardware Manual page 827

Item
Figure 14.16 Flowchart Example
of Data Reception
Figure 14.17 Flowchart Example
of Simultaneous
Transmission/Reception
Figure 15.1 Block Diagram of A/D
Converter (Unit 0/AD_0)
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Page Revision (See Manual for Details)
543 Deleted
[1]
544 Amended
[1]
Transmission/reception started
[2]
Clear TE and RE in SSER to 0
548 Amended
Start
Initial setting
RE = 1 (receprion started)
Read SSSR
Start
Initial setting
(TE = 1, RE = 1)
Read TDRE in SSSR
Consecutive data
transmission/reception?
No
Read TEND in SSSR
No
TEND = 1?
Yes
Clear TEND in SSSR to 0
No
Has the 1 bit transfer
period elapsed?
Yes
End transmission/reception
AV 0
CC
10-bit D/A
AV
SS
Rev. 3.00 Mar. 14, 2006 Page 789 of 804
Error processing
REJ09B0104-0300