Renesas H8SX/1520 Series Hardware Manual page 34

Table 5.2
Table 5.3
Table 5.4
Table 5.5
Table 5.6
Table 5.7
Table 5.8
Section 6 Bus Controller (BSC)
Table 6.1
Table 6.2
Table 6.3
Section 7 DMA Controller (DMAC)
Table 7.1
Table 7.2
Table 7.3
Table 7.4
Table 7.5
Table 7.6
Section 8 I/O Ports
Table 8.1
Table 8.2
Table 8.3
Table 8.4
Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.1
Table 9.2
Table 9.3
Table 9.4
Table 9.5
Table 9.6
Table 9.7
Table 9.8
Table 9.9
Table 9.10
Table 9.11
Table 9.12
Table 9.13
Table 9.14
Rev. 3.00 Mar. 14, 2006 Page xxxiv of xxxviii
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Interrupt Sources, Vector Address Offsets, and Interrupt Priority........................ 105
Interrupt Control Modes ....................................................................................... 112
Interrupt Response Times ..................................................................................... 117
Number of Execution States in Interrupt Handling Routine ................................. 118
Interrupt Source Selection and Clear Control ....................................................... 119
CPU Priority Control ............................................................................................ 121
Example of Priority Control Function Setting and Control State ......................... 121
Synchronization Clocks and Their Corresponding Functions............................... 128
Number of Access Cycles for On-Chip Memory Spaces...................................... 129
Number of Access Cycles for Registers of On-Chip Peripheral Modules ............ 129
Data Access Size, Valid Bits, and Settable Size ................................................... 142
Settings and Areas of Extended Repeat Area ....................................................... 156
Transfer Modes..................................................................................................... 157
List of On-chip module interrupts to DMAC........................................................ 167
Priority among DMAC Channels.......................................................................... 181
Interrupt Sources and Priority............................................................................... 200
Port Functions....................................................................................................... 205
Register Configuration in Each Port ..................................................................... 210
Input Pull-Up MOS State...................................................................................... 214
Available Output Signals and Settings in Each Port............................................. 239
Unit Configuration for Each Product.................................................................... 252
TPU Functions (Unit 0) ........................................................................................ 252
TPU Functions (Unit 1) ........................................................................................ 254
Pin Configuration.................................................................................................. 258
CCLR2 to CCLR0 (Channels 0 and 3) ................................................................. 266
CCLR2 to CCLR0 (Channels 1, 2, 4, and 5) ........................................................ 266
Input Clock Edge Selection .................................................................................. 267
TPSC2 to TPSC0 (Channel 0) .............................................................................. 267
TPSC2 to TPSC0 (Channel 1) .............................................................................. 267
TPSC2 to TPSC0 (Channel 2) .............................................................................. 268
TPSC2 to TPSC0 (Channel 3) .............................................................................. 268
TPSC2 to TPSC0 (Channel 4) .............................................................................. 269
TPSC2 to TPSC0 (Channel 5) .............................................................................. 269
MD3 to MD0 ........................................................................................................ 271