Renesas H8SX/1520 Series Hardware Manual page 529

(1)
CPU interrupt source settings
The CPU interrupt source is set by the interrupt mask register (IMR) and mailbox interrupt mask
register (MBIMR). Transmission acknowledge and transmission abort acknowledge interrupts can
be generated for individual mailboxes in the mailbox interrupt mask register (MBIMR).
(2)
Arbitration field setting
The arbitration field is set by the message control registers MCx[5] to MCx[8] in a transmit
mailbox. For a standard format, an 11-bit identifier (ID-28 to ID-18) and the RTR bit are set, and
the IDE bit is cleared to 0. For an extended format, a 29-bit identifier (ID-28 to ID-0) and the RTR
bit are set, and the IDE bit is set to 1.
(3)
Control field setting
In the control field, the byte length of the data to be transmitted is set within the range of zero to
eight bytes. The register to be set is the message control register MCx[1] in a transmit mailbox.
(4)
Data field setting
In the data field, the data to be transmitted is set within the range zero to eight. The registers to be
set are the message data registers MDx[1] to MDx[8]. The byte length of the data to be transmitted
is determined by the data length code in the control field. Even if data exceeding the value set in
the control field is set in the data field, up to the byte length set in the control field will actually be
transmitted.
(5)
Message transmission
If the corresponding mailbox transmit wait bit (TXPR1 to TXPR15) in the transmit wait register
(TXPR) is set to 1 after message control and message data registers have been set, the message
enters transmit wait state. If the message is transmitted error-free, the corresponding acknowledge
bit (TXACK1 to TXACK15) in the transmit acknowledge register (TXACK) is set to 1, and the
corresponding transmit wait bit (TXPR1 to TXPR15) in the transmit wait register (TXPR) is
automatically cleared to 0. Also, if the corresponding bit (MBIMR1 to MBIMR15) in the mailbox
interrupt mask register (MBIMR) and the mailbox empty interrupt bit (IRR8) in the interrupt mask
register (IMR) are both simultaneously set to enable interrupts, interrupts may be sent to the CPU.
If transmission of a transmit message is aborted in the following cases, the message is
retransmitted automatically:
• CAN bus arbitration failure (failure to acquire the bus)
• Error during transmission (bit error, stuff error, CRC error, frame error, or ACK error)
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Section 13 Controller Area Network (HCAN)
Rev. 3.00 Mar. 14, 2006 Page 491 of 804
REJ09B0104-0300