Renesas H8SX/1520 Series Hardware Manual page 188

Section 7 DMA Controller (DMAC)
Bit Bit Name
2 DMAP2
1 DMAP1
0 DMAP0
Note: * Only 0 can be written to, to clear the flag.
Rev. 3.00 Mar. 14, 2006 Page 150 of 804
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Initial
Value R/W Description
0 R/W DMA Priority Level 2 to 0
0 R/W Select the priority level of the DMAC. When the CPU
has priority over the DMAC, the DMAC masks a transfer
0 R/W
request and waits for the timing when the CPU priority
becomes lower than the DMAC priority. The priority
levels can be set to the individual channels. This bit is
valid when the CPUPCE bit in CPUPCR is set to 1.
000: Priority level 0 (low)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (high)